1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an SOI device and a method for fabricating the same in which floating body effect is reduced and the performance is thus improved.
2. Discussion of the Related Art
A background art SOI device will be described with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view of a background art SOI device. This background art SOI device, constituting a CMOS transistor, includes a buried oxide film 2 formed on a semiconductor substrate 1, a p type semiconductor layer 4 doped with p type ions and formed on a predetermined area of the buried oxide film 2, and an n type semiconductor layer 5 formed on a predetermined area of the buried oxide film 2 and spaced apart from the p type semiconductor layer 4. An isolation oxide film 3 is formed to have a higher height than the p and n type semiconductor layers 4 and 5 to isolate the p type semiconductor layer 4 from the n type semiconductor layer 5.
A gate-oxide film 6 and a first gate electrode 7a are formed on a predetermined area of the p type semiconductor layer 4. Source/drain regions 8a/8b having an LDD structure are formed in the p type semiconductor layer 4 at both sides of the first gate electrode 7a. Sidewall spacers are formed on the both sides of the first gate electrode 7a.
A gate oxide film 6 and a second gate electrode 7b are formed on a predetermined area of the n type semiconductor layer 5. Source/drain regions 9a/9b having an LDD structure are formed in the n type semiconductor layer 5 at both sides of the second gate electrode 7b. Sidewall spacers are formed on both sides of the second gate electrode 7b.
While an NMOS transistor is formed in the p type semiconductor layer 4, a PMOS transistor is formed in the n type semiconductor layer 5.
An interlayer insulating film 10 are formed to have contact holes on the source/drain regions 8a/8b and 9a/9b and the first and second gate electrodes 7a and 7b. Line layers 11a, 11b, 11c, 11d, 11e, and 11f, are formed in the contact holes and on the interlayer insulating film adjoining to the contact holes.
As described above, p and n type semiconductor layers 4 and 5, which serve as channels of NMOS transistor and PMOS transistor, float in the background art SOI device.
Such a background art SOI device has the following problems. A p type semiconductor layer and an n type semiconductor layer, serving as channels of NMOS and PMOS transistors, are electrically connected, yet float, so that break down voltage is reduced and floating body effect is generated so that errors in current-voltage curve are generated. Accordingly the operation characteristic becomes inferior.